1. Field of the Invention
This invention relates to a field effect transistor (FET) circuit for converting bipolar logic levels to FET logic levels. More particularly, this invention relates to a circuit for converting transistor transistor logic (TTL logic levels) to FET logic levels.
2. Description of the Prior Art
A number of circuits are known in the prior art for converting TTL logic levels to FET logic levels. The need for such converter circuits arises because both TTL and FET circuits are used in modern data processing systems. An interface circuit to convert from one set of logic voltage levels to another is therefore a standard requirement. Main memories for data processing systems are frequently fabricated with FETs in integrated circuit form and have advantages of dense integration and low power dissipation. Bipolar logic circuits, however, have a higher operating speed and it therefore becomes advantageous to form the control logic circuits for the main memory from bipolar transistors in circuit configurations such as TTL. Thus, there is a continuing need for improved interfaces between bipolar and FET circuits to overcome otherwise incompatible logic voltage levels.
As mentioned, one form of digital circuit fabricated from bipolar transistors is the so called TTL logic system. In TTL, one binary state, e.g. the logic "0" is usually represented by a voltage in the range of 0 to 0.8 volts. The other binary state, e.g. the logic "1" is represented by a voltage in the range of 2.0 volts to as high as 5.5 volts. By way of comparison, FET circuits normally operate in the range of 0 to 8.5 volts.
The prior art is exemplified by E. ARAI and N. IEDA in the June 1978 issue of the IEEE Journal of Solid-State Circuits, Vol SC-13, No. 3, pages 333-338. This article describes a circuit for converting TTL levels into FET levels particularly at section IV, pages 335 and 336 and FIG. 5. The field effect transistors used in this published level converter are assumed to have a threshold voltage VT of 0.8 volts which is near the maximum value of 0.8 volts for the down level TTL signal. For this reason, in order to prevent the input FET from becoming conductive when noise pulses are added to this already high level, the source potential of the FET is raised by a voltage divider circuit. Thus, the input FET becomes conductive only when the applied signal is higher than the sum of its source bias and its threshold voltage. Although this technique eliminates the effect of noise pulses on the switching characteristics of the input FET, it also prevents the FET from conducting until it receives an input signal sufficiently high to overcome the effect of the bias on the source of the input FET. For example, if the source of the input FET is raised to 0.7 volts and the threshold voltage is 0.8 volts, then the input must be over 1.5 volts to cause the input FET to conduct. A disadvantage of this arrangement becomes apparent when it is noted that the lowest possible up level of a TTL signal is 2.0 volts and this 0.5 volts differential (between 2.0 and 1.5) is insufficient to turn the input FET fully on. Thus, the proposed solution to the TTL to FET conversion problem at the low logic level creates another problem at the high logic level. The problem at the high logic level could be solved by a requirement that the lowest possible high logic level be greater than 2.0 volts. This, however, would require still an additional circuit to convert from standard TTL logic levels to this new up level which is greater than 2.0 volts. Another problem that remains unsolved with this particular prior art circuit is that the threshold voltage of FETs fabricated in integrated circuit form cannot be made with consistent thresholds of 0.8 volts. Due to manufacturing tolerances, the threshold voltage of FETs varies significantly from one integrated circuit chip to another.